Paper Details

Communicating Process Architectures (CPA)
 Title: Deriving Stencil Hardware Accelerators from a Single Higher-Order Function
 Conference: Communicating Process Architectures 2014
 Authors: Rinse Wester, Jan Kuper
Computer Architecture for Embedded Systems, CTIT Institute, University of Twente
 Abstract: Stencil computations can be found in a lot of scientific and engineering applications. Parallelization of these applications becomes more and more important in order to keep up with the demand for computing power. FPGAs offer a lot of compute power but are considered hard to program. In this paper, a design methodology based on transformations of higher-order functions is introduced to facilitate the parallelization process. Using this methodology, efficient FPGA hardware architectures are derived achieving good performance. Two architectures for heat flow computations are synthesized for FPGA and evaluated. To show the general applicability of the design methodology, several applications have been implemented. 

BibTeX Entry

Full paper