Paper Details

Communicating Process Architectures (CPA)
 Title: T42 – Transputer Design in FPGA
 Conference: Communicating Process Architectures 2014
 Authors: Uwe Mielkea, Martin Zabelb, Michael Bruestlec
(a) Infineon Technologies
(b) Institute of Computer Engineering, Technische Universität Dresden
(c) Electronics Engineer
 Abstract: This fringe paper is discussing the current status of a still ongoing T42x compatible 3 stage pipelined Transputer design in FPGA. The intention of this small project is to provide the VHDL as open source, so that many cores can be loaded into a FPGA board for education or exploration purposes. To evaluate the public attraction of such a Transputer design today, a performance outlook of our T42 design and potential successors is projected into a target corridor and compared with other available softcores in FPGA. Our conclusion is: w/o a future design roadmap the T42 will remain academic, but once improved in architecture it can compete with any RISC softcore CPU. This is challenging goal ... any support is welcome. 

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