Paper Details

Communicating Process Architectures (CPA)
 Title: Discrete Event-based Neural Simulation using the SpiNNaker System
 Conference: Communicating Process Architectures 2015
 Authors: Andrew Browna, Jeff Reeveb, Steve Furberc
(a) University of Southampton, UK, University of Southampton
(b) Department of Electronics & Computer Science, University of Southampton
(c) School of Computer Science, Univeristy of Manchester
 Abstract: SpiNNaker is a computing system composed of over a million ARM cores, embedded in a bespoke asynchronous communication fabric. The physical realization of the system consist of 57600 nodes (a node is a silicon die), each node containing 18 ARM cores and a routing engine. The communication infrastructure allows the cores to communicate via short, fixed-length (40- or 72-bit), hardware-brokered packets. The packets find their way through the network in a sequence of hops, and the specifics of each route are held (distributed) in the route engines, not unlike internet routing. On arrival at a target core, a hardware-triggered interrupt invokes code to handle the incoming packet. Within this computing model, the state of the system-under-simulation is distributed, held in memory local to the cores, and the topology is also distributed, held in the routing engine internal tables. The message passing is non-deterministic and non-transitive, there is no memory coherence between the core local memories, and there is no global synchronization. This paper shows how such a system can be used to simulate large systems of neurons using discrete event-based techniques. More notably, the solution time remains approximately constant with neural system size as long as sufficient hardware cores are available. 
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