Paper Details

Communicating Process Architectures (CPA)
 Title: SystemVerilogCSP: Modeling Digital Asynchronous Circuits Using SystemVerilog Interfaces
 Conference: Communicating Process Architectures 2011
 Authors: Arash Saifhashemi, Peter A. Beerel
Ming Hsieh Department of Electrical Engineering, University of Southern California
 Abstract: This paper describes how to model channel-based digital asynchronous circuits using SystemVerilog interfaces that implement CSP-like communication events. The interfaces enable explicit handshaking of channel wires as well as abstract CSP events. This enables abstract connections between modules that are described at different levels of abstraction facilitating both verification and design. We explain how to model one-to-one, one-to-many, one-to-any, any-to-one, and synchronized channels. Moreover, we describe how to split communication actions into multiple parts to more accurately model less concurrent handshaking protocols that are commonly found in many asynchronous pipelines. 

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