Communicating Process Architectures 2016: Programme

Schedule

 
 Sunday, August 21st, 2016
 19:00           Dinner (Caféen? Bar, Building 4, Universitetsparken 15) [Note: the question-mark is part of the Café name, not an uncertainty for the location.]
 20:30           Fringe Session 1 (Caféen? Bar)
Note: because of the nature of the Fringe, the following items are provisional; more may be added and the ordering may change.
Messing Around with Timeouts. In Contracts? (Abstract)
Øyvind Teig
Autronica Fire and Security AS
T42 Transputer Design in FPGA (Year Two Design Status Report) (Abstract)
Uwe Mielkea, Martin Zabelb, Michael Bruestlec
(a) Infineon Technologies
(b) Institute of Computer Engineering, Technische Universität Dresden
(c) Electronics Engineer
Concurrency: Quit Obsessing about Your Code and Start Worrying about Your Data! (Abstract)
Brian Vinter
Niels Bohr Institute, University of Copenhagen
Visualisation Facilities of the Graphical CSP tool TERRA (Abstract)
Zhou Lu
Robotics and Mechatronics, CTIT Institute, University of Twente
Distributed Computing on a (tiny) Budget: Building a Raspberry Pi Zero Microcluster (Abstract)   (Best fringe)
Richard Miller
Miller Research, Oxford, England, Miller Research
 23:00           Bar closes
 
 Monday, August 22nd, 2016
 08:30           Registration (Auditorium 07, H.C. Ørsted Institute (aka HCØ), Universitetsparken 5)
 09:15           Welcome (Brian Vinter)
 Session 1 (Auditorium 07, HCØ)
 09:30           JVMCSP – Approaching Billions of Processes on a Single-Core JVM (Abstract)
Jan Bækgaard Pedersen, Cabel Shrestha
Department of Computer Science, University of Nevada Las Vegas
 10:00           Communicating Generators in JavaScript (Abstract)   (Best student paper)
Kurt Micallef, Kevin Vella
Department of Computer Science, University of Malta
 10:30           Tea/coffee
 Session 2 (Auditorium 07, HCØ)
 11:00           Connecting Two Robot-Software Communicating Architectures: ROS and LUNA (Abstract)   (Best paper)
W. Mathijs van der Werf, Jan F. Broenink
Robotics and Mechatronics, CTIT Institute, University of Twente
 11:30           Simulation and Visualisation Tool Design for Robot Software (Abstract)
Zhou Lu, Tjaling Ran, Jan F. Broenink
Robotics and Mechatronics, CTIT Institute, University of Twente
 12:00           High Performance Tape Streaming in Tapr (Abstract)
Klaus Birkelund Jensen, Brian Vinter
Niels Bohr Institute, University of Copenhagen
 12:30           Lunch (BioCenter, Ole Maaløes Vej 5)
 Session 3 (Auditorium 07, HCØ)
 14:00           Extensions to the Concurrent Communications Library (Abstract)
Kenneth Skovhede, Brian Vinter
Niels Bohr Institute, University of Copenhagen
 14:30           Workshop Session 1
Building a Sensor System for a Large Scale Arctic Observatory (Abstract)
John Markus Bjørndalena, Otto J. Anshusa, Tore Brox-Larsena, Phuong Hoai Haa, Rolf Anker Imsb, Jane Uhd Jepsenc, Siw Turid Killengreenb, Eivind Flittie Kleivenb, Eeva Marjatta Soininenb, Nigel Gilles Yoccozb, Alexander Horscha
(a) Department of Computer Science, University of Tromsø
(b) Department of Arctic and Marine Biology, University of Tromsø
(c) Norwegian Institute for Nature Research
 15:30           Tea/coffee
 18:00           Conference dinner (Restaurant HØST, Nørre Farimagsgade 41)
 20:30           Bar (Ørsted Ølbar, Nørre Farimagsgade)
 
 Tuesday, August 23rd, 2016
 Session 4 (Auditorium 07, HCØ)
 09:30           Keynote Address 1
Computational Challenges for Climate Modelling (Abstract)
Markus Jochum
Niels Bohr Institute, University of Copenhagen
 10:30           Tea/coffee
 Session 5 (Auditorium 07, HCØ)
 11:00           Broadcasting in CSP Style Programming (Abstract)
Brian Vinter, Kenneth Skovhede, Mads Ohm Larsen
Niels Bohr Institute, University of Copenhagen
 11:30           Mapping CSP Models for Embedded Control Software to Hardware Using CλaSH (Abstract)
Frits P. Kuipersa, Rinse Westerb, Jan Kuperb, Jan F. Broeninka
(a) Robotics and Mechatronics, CTIT Institute, University of Twente
(b) Computer Architecture for Embedded Systems, CTIT Institute, University of Twente
 12:00           VHDL Generation From Python Synchronous Message Exchange Networks (Abstract)
Truls Asheim, Kenneth Skovhede, Brian Vinter
Niels Bohr Institute, University of Copenhagen
 12:30           Lunch (BioCenter, Ole Maaløes Vej 5)
 Session 6 (Auditorium 07, HCØ)
 14:00           Communicating Connected Components: Extending Plug and Play to Support Skeletons (Abstract)
Kevin Chalmersa, Jon Kerridgea, Jan Bækgaard Pedersenb
(a) School of Computing, Edinburgh Napier University
(b) Department of Computer Science, University of Nevada Las Vegas
 14:30           Asynchronous Readers and Writers (Abstract)
Antoon H. Boode, Jan F. Broenink
Robotics and Mechatronics, CTIT Institute, University of Twente
 15:00           Tea/coffee
 Session 7 (Auditorium 07, HCØ)
 16:00           Development and Evaluation of a Modern C++CSP Library (Abstract)
Kevin Chalmers
School of Computing, Edinburgh Napier University
 16:30           CPA AGM and awards
 17:00           End of CPA 20161
  Keynote Presentations
 
    Computational Challenges for Climate Modelling
      Markus Jochum
       Niels Bohr Institute, University of Copenhagen

Abstract:  Numerical simulation of Earth's climate is one branch of computational fluid dynamics. This community faces two key challenges. Firstly, the turbulence closure problem has still not been solved. Therefore more accurate simulations require higher spatial resolution. Secondly, testing the fidelity of our climate models for a future warmer world can only be done by reproducing past warm periods. This requires much faster integrations, which also need to include Earth's full carbon biochemistry. The former requires massively parallel computing architectures and a data infrastructure that can manage rates of 1 Tb/day; the latter requires codes or chips that are an order of magnitude faster than what is currently available. I will briefly describe the evolution of the developments of climate models, show recent results with global geostrophic turbulence resolving models, and outline some ideas of how to structure the community's resources in the future.

  Papers
 
    JVMCSP – Approaching Billions of Processes on a Single-Core JVM
      Jan Bækgaard Pedersen, Cabel Shrestha
       Department of Computer Science, University of Nevada Las Vegas

Abstract:  In this paper we present the JVMCSP – a runtime system for the JVM and a code generator in the ProcessJ compiler. ProcessJ is a new process-oriented language with a Java-like syntax and CSP semantics. ProcessJ compiles to a number of different runtimes and in this paper focuses on the JVM runtime. The approach followed in the implementation is inspired by previous prototype-work we have done, but in this paper we closely look at the actual implementation and how it differed from our previous assumptions. We also present a number of results that highlight the capabilities of our code generator and runtime. We show that the runtime has a low overhead and we managed to run a program on a single core with 480,900,001 processes and a total of over 1.4 billion runtime objects on the JVM heap.

    Communicating Generators in JavaScript
      Kurt Micallef, Kevin Vella
       Department of Computer Science, University of Malta

Abstract:  This paper outlines the design, performance, and use of an application programming interface and library for concurrent programming with CSP in JavaScript. The implementation harnesses ECMAScript 6 Generators to provide co-operative scheduling and channel communication within a single JavaScript engine. External channels lie atop WebSockets, amongst other web technologies, to enable multicore and distributed execution across standard web browsers and Node.js servers. Low-level benchmarks indicate that scheduling and messaging performance is within reasonable expectation for this dynamic and diverse execution environment. Sample code snippets highlight the applicability of CSP to contemporary web development in hiding the location of computation and state through the channel abstraction. The call-back hell scenario is alleviated through the use of sequential-style CSP code rather than callbacks predominantly used in the language and the possibility of performing parallel and scientific computing is explored with promising results. Finally, the limitations of the present design are discussed, and possible enhancements such as the dynamic migration of state and code are considered.

    Connecting Two Robot-Software Communicating Architectures: ROS and LUNA
      W. Mathijs van der Werf, Jan F. Broenink
       Robotics and Mechatronics, CTIT Institute, University of Twente

Abstract:  Two current trends in modern robotics and other cyber-physical systems seem to conflict: the desire for better interaction with the environment of the robot increases the needed computational power to extract useful data from advanced sensors. This conflicts with the need for energy efficiency and mobility of the setups. A solution for this conflict is to use a distribution over two parallel systems: offloading a part of the complex and computationally expensive task to a base station, while timing-sensitive parts remain close to the robotic setup on an embedded processor. In this paper, a way to connect two of such systems is presented: a bridge is made between the Robotic Operating System (ROS), a widely used open source environment with many algorithms, and the CSP-execution engine LUNA. The bridge uses a (wireless) network connection, and provides a generic and reconfigurable way of connecting these two environments. The design, implementation in both environments, and tests characterizing the bridge are described in this paper.

    Simulation and Visualisation Tool Design for Robot Software
      Zhou Lu, Tjaling Ran, Jan F. Broenink
       Robotics and Mechatronics, CTIT Institute, University of Twente

Abstract:  Modern embedded systems are designed for multiple and increasingly demanding tasks. Complex concurrent software is required by multi-task automated service robotics for implementing their challenging (control) algorithms. TERRA is a Communicating Sequential Processes Cyber-Physical System (CPS) co-design. Moreover, a visualisation for the simulation is designed as well to provide animation facilities which enable users to visually trace simulated execution flows. Finally, we use an example to test the hybrid simulation approach as well as visualisation facilities. It is showed that the simulation approach is sufficient and visualisation works as intended.

    High Performance Tape Streaming in Tapr
      Klaus Birkelund Jensen, Brian Vinter
       Niels Bohr Institute, University of Copenhagen

Abstract:  In this paper we describe the design and implementation of the Tapr high performance tape streaming system. Tapr consists of a number of basic processes interacting though message passing on CSP-style communications channels. The system is highly concurrent, uses synchronous as well as asynchronous coordination without the need for complex usage of traditional locks. The system scales to and beyond contemporary enterprise automated tape libraries by representing each and every part of the tape library as a communicating process. This includes the robot changer, each tape drive, all clients and even the loaded tape media. We show how such an implementation can be done in the Go programming language with relative ease by utilizing the concurrency primitives included in the base language. We also describe how complex cancellation and timeout handling can be handled directly in the language. Finally, we present a number of benchmarks designed to show that the communicating process architecture does not impose any measurable overhead, but rather allows the system to scale to a high number of clients and devices using a simple and intuitive process-based design.

    Extensions to the Concurrent Communications Library
      Kenneth Skovhede, Brian Vinter
       Niels Bohr Institute, University of Copenhagen

Abstract:  This paper presents updates and measurements for the Concurrent Communications Library, CoCoL, which is a CSP inspired library targeting C# and other languages running on the Common Language Runtime, also known as .Net. We describe the new library interface methods that simplify writing correct, encapsulated and compositional networks. We also describe an extension to the library, which enables communication over network connections and measure the performance.

    Building a Sensor System for a Large Scale Arctic Observatory
      John Markus Bjørndalena, Otto J. Anshusa, Tore Brox-Larsena, Phuong Hoai Haa, Rolf Anker Imsb, Jane Uhd Jepsenc, Siw Turid Killengreenb, Eivind Flittie Kleivenb, Eeva Marjatta Soininenb, Nigel Gilles Yoccozb, Alexander Horscha
       (a) Department of Computer Science, University of Tromsø
       (b) Department of Arctic and Marine Biology, University of Tromsø
       (c) Norwegian Institute for Nature Research

Abstract:  The Climate-ecological Observatory for Arctic Tundra (COAT) is a longterm research initiative for real time detection, documentation and understanding of climate impacts on terrestrial arctic ecosystems. COAT is a collaboration of several Norwegian research institutions under the umbrella of FRAM – High North Centre for Climate and Environment. The study areas include the bioclimatic extremes of the terrestrial Arctic, low arctic coast of Norway and high arctic Svalbard. An important part of the observatory is sensors placed in the environment to observe wildlife and plants. Current sensor packages are fairly robust and work well for small to medium scale deployment. For larger scales, however, there is a clear demand for better management and control. This paper summarises some current experiences with deploying cameras and some of the challenges that we intend to address in an up-coming project where we aim to increase the capability of scientists to handle a larger number and diversity of sensor types and variation in deployment while minimising human traffic and impact in the monitored environments. To build this type of observatory at increasing scales, we expect to use robust programming architectures, open modular sensor packages, on-line processing, monitoring and configuration management and a range of communication technologies to cope with variations in connectivity.

    Broadcasting in CSP Style Programming
      Brian Vinter, Kenneth Skovhede, Mads Ohm Larsen
       Niels Bohr Institute, University of Copenhagen

Abstract:  While CSP only models process-to-process rendezvous style message passing, several CSP type programming libraries offer more powerful mechanisms, such as buffered channels, multiple receivers and even multiple senders on a single channel. This work investigates the possible variations of a one-to-all broadcasting channel. We discuss the different semantic meanings of broadcasting and show three different possible solutions for adding broadcasting to CSP style programming.

    Mapping CSP Models for Embedded Control Software to Hardware Using CλaSH
      Frits P. Kuipersa, Rinse Westerb, Jan Kuperb, Jan F. Broeninka
       (a) Robotics and Mechatronics, CTIT Institute, University of Twente
       (b) Computer Architecture for Embedded Systems, CTIT Institute, University of Twente

Abstract:  Current robotic systems are becoming more and more complex. This is due to an increase in the number of subsystems that have to be controlled from a central processing unit as well as more stringent requirements on stability, reliability and timing. A possible solution is to offload computationally demanding parts to an FPGA controlled by the main processor. The parallel nature of FPGAs makes achieving hard real-time guarantees more easy. Additionally, due its parallel and sequential constructs, CSP matches structurally with an FPGA. In this paper, a CSP to hardware mapping is proposed where key CSP structures are translated to hardware using the functional language CλaSH. The CSP structures can be designed using the TERRA tool chain while CλaSH code is generated for implementing hardware. The functionality of the CSP mapping is illustrated using some producer-consumer examples. In this paper, the design, implementation and tests are presented. Future work is to implement the ALT construct and generate token diagrams for user understanding.

    VHDL Generation From Python Synchronous Message Exchange Networks
      Truls Asheim, Kenneth Skovhede, Brian Vinter
       Niels Bohr Institute, University of Copenhagen

Abstract:  The Synchronous Message Exchange, SME, is a programming model that both resembles communication in hardware, and can be implemented as a CSP network. This paper extends on previous work for modeling hardware-like programs using SME in Python, with the addition of a source-to-source compiler that converts an SME network implemented in Python to an equivalent implementation in VHDL. We describe the challenges, constraints, and solutions involved in translating a highly dynamical language like Python into the hardware-like VHDL language. We also show how the approach can assist in further VHDL refinement by generating tedious test bench code, such that VHDL designs can be simulated and verified with vendor supplied simulation and synthesis tools.

    Communicating Connected Components: Extending Plug and Play to Support Skeletons
      Kevin Chalmersa, Jon Kerridgea, Jan Bækgaard Pedersenb
       (a) School of Computing, Edinburgh Napier University
       (b) Department of Computer Science, University of Nevada Las Vegas

Abstract:  For a number of years, the Communicating Process Architecture (CPA) community have developed languages and runtimes supporting message passing concurrency. For these we always provide a set of reusable processes called plug and play. These components provide a rich set of functions to CPA programmers, enabling them to develop applications in interesting new ways. In this paper, we describe recent work in taking the plug and play ideology and applying it to the area of algorithmic skeletons. We have based our work on the RISC-pb2l specifications of Danelutto et al. to provide a base set of skeletal components, focusing on the communication behaviours they exhibit.

    Asynchronous Readers and Writers
      Antoon H. Boode, Jan F. Broenink
       Robotics and Mechatronics, CTIT Institute, University of Twente

Abstract:  Reading and writing is modelled in CSP using actions containing the symbols ? and !. These reading and writing actions are synchronous and there is a one-to-one relationship between occurrences of pairs of these actions. It is cumbersome to ease the restriction of synchronous execution of the read and write actions. For this reason, we introduce the half-asynchronous parallel operator that acts on actions containing the symbols ¿ and ¡ and study the impact on a Vertex Removing Synchronised Product.

    Development and Evaluation of a Modern C++CSP Library
      Kevin Chalmers
       School of Computing, Edinburgh Napier University

Abstract:  Although many CSP inspired libraries exist, none yet have targeted modern C++ (C++11 onwards). The work presented has a main objective of providing a new C++CSP library which adheres to modern C++ design principles and standards. A secondary objective is to develop a library that provides simple message passing concurrency in C++ using only the standard library. The library is evaluated in comparison to JCSP using microbenchmarks. CommsTime and StressedAlt are used to determine the properties of coordination time, selection time, and maximum process count. Further macrobenchmarks, Monte Carlo π and Mandelbrot, are gathered to measure potential speedup with C++CSP. From the microbenchmarks, it is shown that C++CSP performs better than JCSP in communication and selection operations and, due to using the same threading model as JCSP, can create an equal number of processes. From the macrobenchmarks, it is shown that C++CSP can provide an almost six times speedup for computation based workloads, and a four times speedup for memory based workloads. The implementation of move semantics in channels have provided suitable enhancements to overcome data copy costs in channels. Therefore, C++CSP is considered a useful addition to the range of CSP libraries available. Future work will investigate other benchmarks within C++CSP as well as development of networking and skeleton based frameworks.

  Fringe Presentations
 
    Messing Around with Timeouts. In Contracts?
      Øyvind Teig
       Autronica Fire and Security AS

Abstract:  Many (embedded) systems are often designed with timeouts at places where they are not needed or even wrong. When there is a timeout, it may break the very idea of how a contract should be: without timeout. For example, some response from an internal communication driver (that handles an external connection) may be awaited for with a timeout – when it might be better just to wait for a proper response from the driver telling that the connection is indeed broken (i.e. that the driver performs the timeout). Timeout has a dimension of layer associated with it. For the above example, the timeout was properly handled by the driver to detect the broken connection, not by the client. Timeouts are, of course, appropriate for periodic processes like blinking an LED or pinging a line, where the connotation of a timer is used. However, having timeouts between internal communicating processes quickly makes matters difficult. We define timeout not to be part of a contract per se (even if this is rather contrary to judicial understanding of the term, where an expiration date often is necessary). In design by contract, failed critical assertions may be handled locally and the whole system may restart – best detected during testing, before final release. However, formally verifying a system or using deadlock-free patterns to ensure a correct design is considered good. Requiring (over an external link that has a timeout of 5 seconds) that a heating element must increase the temperature after the push of a button (within 4 seconds) and a response must be shown on the display (by 3 seconds) should trigger a (hopefully) interesting and useful discussion of the specifications. We shall also consider a process network (discussed in the blog note mentioned below) which contains a possibly unnecessary timer, without which the system might be much simplified.

    T42 Transputer Design in FPGA (Year Two Design Status Report)
      Uwe Mielkea, Martin Zabelb, Michael Bruestlec
       (a) Infineon Technologies
       (b) Institute of Computer Engineering, Technische Universität Dresden
       (c) Electronics Engineer

Abstract:  This fringe session will present the design progress of our IMS-T425 compatible Transputer design in FPGA. The 32-bit CPU + Memory interface (2x8kB) are in stable working condition. 117 instructions (from 123+7) are almost implemented in 460 lines of uCode: for example, TASM loops including interruptible MOVE(s) can be simulated some 100 clock cycles. Timer(s) are running. The System control unit allows error mode, MOV-bit and events. Some still open questions around scheduler micro-code and link interaction will be discussed.

    Concurrency: Quit Obsessing about Your Code and Start Worrying about Your Data!
      Brian Vinter
       Niels Bohr Institute, University of Copenhagen

Abstract:  Concurrency is commonly used for coordinating events that are non-deterministic in nature, sensors, transaction systems and games to mention a few. However, in the era of Big Data, concurrency has a whole new dimention to the need for concurrency. With thousands of concurrent operations with highly asynchronous completion times, an efficient concurrency control system is essential for performance. This talk will show the challenge and introduce one idea towards concurrency as a mechanism for Big Data access.

    Visualisation Facilities of the Graphical CSP tool TERRA
      Zhou Lu
       Robotics and Mechatronics, CTIT Institute, University of Twente

Abstract:  Graphs, animations, and visualisations are known to be valuable forms of presenting results of experiments, both simulation and real-life experiments. For CSP-based concurrent programs, the state of processes, CSP constructs and channels are relevant to show. For proper feedback, these can best be related to the form in which the program was entered by the user. In the case of the TERRA graphical CSP tool, feedback is given by colouring the diagram elements according to the specific state they are in. Next to that, a textual log of events is produced, giving more details relevant in the development process. In this Fringe session, we demonstrate this visualisation facility of our graphical CSP tool TERRA. A paper reporting context and technical details of this tool is presented elsewhere in these Proceedings.

    Distributed Computing on a (tiny) Budget: Building a Raspberry Pi Zero Microcluster
      Richard Miller
       Miller Research, Oxford, England, Miller Research

Abstract:  The small, low-cost and tinkering-friendly Raspberry Pi computer board has been used as the basis for a variety of distributed computing clusters built by research groups and individuals for experimental and pedagogical use. The new Raspberry Pi Zero model is smaller, consumes less power, and costs only $5.00 (when supplies are available), but lacks the built-in ethernet interface of its larger predecessors. Making a virtue of necessity, an Altera Cyclone II FPGA on an inexpensive development board can be used to provide the communication fabric for a pocket-sized Raspberry Pi Zero cluster, avoiding the need for bulky network cables and routers, and enabling experimentation with different networking architectures which may be more suited to fine-grained closely-coupled distributed computations than the usual TCP/IP over commodity ethernet. (Work in progress.)